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features and benefits ? low r ds(on) outputs ? automatic current decay mode detection/selection ? mixed and slow current decay modes ? synchronous rectification for low power dissipation ? internal uvlo ? crossover-current protection ? 3.3 and 5 v compatible logic supply ? thin profile qfn and tssop packages ? thermal shutdown circuitry ? short-to-ground protection ? shorted load protection ? low current sleep mode, < 10 a ? no smoke no fire (nsnf) compliance (et package) description the a4985 is a complete microstepping motor driver with built-in translator for easy operation. it is designed to operate bipolar stepper motors in full-, half-, quarter-, and eighth-step modes. step modes are selectable by msx logic inputs. it has an output drive capacity of up to 35 v and 1 a. the a4985 includes a fixed off-time current regulator which has the ability to operate in slow or mixed decay modes. the et package meets customer requirements for no smoke no fire (nsnf) designs by adding no-connect pins between critical output, sense, and supply pins. so, in the case of a pin-to-adjacent-pin short, the device does not cause smoke or fire. additionally, the device does not cause smoke or fire when any pin is shorted to ground or left open. the translator is the key to the easy implementation of the a4985. simply inputting one pulse on the step input drives the motor one microstep. there are no phase sequence tables, high frequency control lines, or complex interfaces to program. the a4985 interface is an ideal fit for applications where a complex microprocessor is unavailable or is overburdened. during stepping operation, the chopping control in the a4985 automatically selects the current decay mode, slow or mixed. in mixed decay mode, the device is set initially to a fast decay for a proportion of the fixed off-time, then to a slow decay for the remainder of the off-time. mixed decay current control results in reduced audible motor noise, increased step accuracy, and reduced power dissipation. 4985-ds, rev. 4 dmos microstepping driver with translator and overcurrent protection continued on the next page? a4985 microcontroller or controller logic v dd vref gnd gnd reset enable sleep dir ms2 ms1 step vbb1 cp1 vcp vreg vdd rosc 5 k 0.22 f 0.22 f 0.1 f0.1 f 100 f cp2 vbb2 out1a out1b sense1 out2a out2b sense2 a4985 typical application diagram packages: 24-contact qfn with exposed thermal pad 4 mm 4 mm 0.75 mm (es package) 24-pin tssop with exposed thermal pad (lp package) 32-contact qfn with exposed thermal pad 5 mm 5 mm 0.90 mm (et package)
dmos microstepping driver with translator and overcurrent protection a4985 2 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com internal synchronous rectification control circuitry is provided to improve power dissipation during pwm operation. internal circuit protection includes: thermal shutdown with hysteresis, undervoltage lockout (uvlo), and crossover-current protection. special power-on sequencing is not required. the a4985 is supplied in three surface mount packages: two qfn packages, the 4 mm 4 mm, 0.75 mm nominal overall height es package, and the 5 mm 5 mm 0.90 mm et package. the lp package is a 24-pin tssop. all three packages have exposed pads for enhanced thermal dissipation, and are lead (pb) free (suffix ?t), with 100% matte tin plated leadframes. description (continued) absolute maximum ratings characteristic symbol notes rating units load supply voltage v bb 35 v output current i out 1 a logic input voltage v in ?0.3 to 5.5 v logic supply voltage v dd ?0.3 to 5.5 v motor outputs voltage ?2.0 to 37 v sense voltage v sense ?0.5 to 0.5 v reference voltage v ref 5.5 v operating ambient temperature t a range s ?20 to 85 oc maximum junction t j (max) 150 oc storage temperature t stg ?55 to 150 oc selection guide part number package packing a4985sestr-t 24-contact qfn with exposed thermal pad 1500 pieces per 7-in. reel a4985settr-t 32-contact qfn with exposed thermal pad 1500 pieces per 7-in. reel a4985slptr-t 24-pin tssop with exposed thermal pad 4000 pieces per 13-in. reel
dmos microstepping driver with translator and overcurrent protection a4985 3 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com functional block diagram sense1 sense2 vreg vcp cp2 control logic dac vdd pwm latch blanking mixed decay dac step dir reset ms1 pwm latch blanking mixed decay current regulator cp1 charge pump r s2 r s1 vbb1 out1a out1b vbb2 out2a out2b 0.1 m f v ref translator gate drive dmos full bridge dmos full bridge 0.1 m f 0.22 m f osc rosc ms2 ref enable sleep ocp ocp
dmos microstepping driver with translator and overcurrent protection a4985 4 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com electrical characteristics 1 at t a = 25c, v bb = 35 v (unless otherwise noted) characteristics symbol test conditions min. typ. 2 max. units output drivers load supply voltage range v bb operating 8 ? 35 v during sleep mode 0 ? 35 v logic supply voltage range v dd operating 3.0 ? 5.5 v output on resistance r ds(on) source driver, i out = ?800 ma ? 700 900 m sink driver, i out = 800 ma ? 700 900 m body diode forward voltage v f source diode, i f = ?800 ma ? ? 1.3 v sink diode, i f = 800 ma ? ? 1.3 v motor supply current i bb f pwm < 50 khz ? ? 4 ma operating, outputs disabled ? ? 2 ma sleep mode ? ? 10 a logic supply current i dd f pwm < 50 khz ? ? 8 ma outputs off ? ? 5 ma sleep mode ? ? 10 a control logic logic input voltage v in(1) v dd ? 0.7 ??v v in(0) ?? v dd ? 0.3 v logic input current i in(1) v in = v dd ? 0.7 ?20 <1.0 20 a i in(0) v in = v dd ? 0.3 ?20 <1.0 20 a microstep select r ms1 ? 100 ? k r ms2 ?50?k logic input hysteresis v hys(in) as a % of v dd 51119% blank time t blank 0.7 1 1.3 s fixed off-time t off osc = vdd or gnd 20 30 40 s r osc = 25 k 23 30 37 s reference input voltage range v ref 0?4v reference input current i ref ?3 0 3 a current trip-level error 3 err i v ref = 2 v, %i tripmax = 38.27% ? ? 15 % v ref = 2 v, %i tripmax = 70.71% ? ? 5 % v ref = 2 v, %i tripmax = 100.00% ? ? 5 % crossover dead time t dt 100 475 800 ns protection overcurrent protection threshold 4 i ocpst 1.1 ? ? a thermal shutdown temperature t tsd ? 165 ? c thermal shutdown hysteresis t tsdhys ?15?c vdd undervoltage lockout v dduvlo v dd rising 2.7 2.8 2.9 v vdd undervoltage hysteresis v dduvlohys ?90?mv 1 for input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin. 2 typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. performance may vary for individual units, within the specified maximum and minimum limits. 3 v err = [(v ref /8) ? v sense ] / (v ref /8). 4 overcurrent protection (ocp) is tested at t a = 25c in a restricted range and guaranteed by characterization.
dmos microstepping driver with translator and overcurrent protection a4985 5 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com thermal characteristics may require derating at maximum conditions characteristic symbol test conditions* value units package thermal resistance r ja es package; estimated, on 4-layer pcb, based on jedec standard 37 oc/w et package; estimated, on 4-layer pcb, based on jedec standard 32 oc/w lp package; on 4-layer pcb, based on jedec standard 28 oc/w *in still air. additional thermal information available on allegro web site. 20 40 60 80 100 120 140 160 180 temperature (c) power dissipation, p d (w) 0.0 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.0 1.5 maximum power dissipation, p d (max) r q ja = 37 oc/w r q ja = 28 oc/w r q ja = 32 oc/w
dmos microstepping driver with translator and overcurrent protection a4985 6 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com figure 1. logic interface timing diagram step t a t d t c ms1, ms2, reset, or dir t b table 1. microstep resolution truth table ms1 ms2 microstep resolution excitation mode l l full step 2 phase h l half step 1-2 phase l h quarter step w1-2 phase h h eighth step 2w1-2 phase time duration symbol typ. unit step minimum, high pulse width t a 1 s step minimum, low pulse width t b 1 s setup time, input change to step t c 200 ns hold time, input change to step t d 200 ns
dmos microstepping driver with translator and overcurrent protection a4985 7 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com device operation. the a4985 is a complete microstepping motor driver with a built-in translator for easy operation with minimal control lines. it is designed to operate bipolar stepper motors in full-, half-, quarter-, and eighth-step resolution modes. the currents in each of the two output full-bridges and all of the n-channel dmos fets are regulated with fixed off-time pwm (pulse width modulated) control circuitry. at each step, the current for each full-bridge is set by the value of its external current-sense resistor (r s1 and r s2 ), a reference voltage (v ref ), and the output voltage of its dac (which in turn is controlled by the output of the translator). at power-on or reset, the translator sets the dacs and the phase current polarity to the initial home state (shown in figures 8 through 11), and the current regulator to mixed decay mode for both phases. when a step command signal occurs on the step input, the translator automatically sequences the dacs to the next level and current polarity. (see table 2 for the current-level sequence.) the microstep resolution is set by the combined effect of the ms1 and ms2 inputs , as shown in table 1. when stepping, if the new output levels of the dacs are lower than their previous output levels, then the decay mode for the active full-bridge is set to mixed. if the new output levels of the dacs are higher than or equal to their previous levels, then the decay mode for the active full-bridge is set to slow. this auto- matic current decay selection improves microstepping perfor- mance by reducing the distortion of the current waveform that results from the back emf of the motor. microstep select (ms1 and ms2). the microstep resolu- tion is set by the voltage on logic inputs ms1 and ms2, as shown in table 1. ms1 has a 100 k pull-down resistance, and ms2 has a 50 k pull-down resistance. when changing the step mode the change does not take effect until the next step rising edge. if the step mode is changed without a translator reset, and abso- lute position must be maintained, it is important to change the step mode at a step position that is common to both step modes in order to avoid missing steps. when the device is powered down, or reset due to tsd or an over current event the translator is set to the home position which is by default common to all step modes. mixed decay operation. the bridge operates in mixed decay mode, at power-on and reset, and during normal running according to the rosc configuration and the step sequence, as shown in figures 8 through 11. during mixed decay, when the trip point is reached, the a4982 initially goes into a fast decay mode for 31.25% of the off-time, t off . after that, it switches to slow decay mode for the remainder of t off . a timing diagram for this feature appears in figure 7. typically, mixed decay is only necessary when the current in the winding is going from a higher value to a lower value as determined by the translator setting. for most loads automatically-selected mixed decay is convenient because it minimizes ripple when the current is rising and prevents missed steps when the current is falling. for some applications where microstepping at very low speeds is necessary, the lack of back emf in the winding causes the current to increase in the load quickly, resulting in missed steps. this is shown in figure 2. by pulling the rosc pin to ground, mixed decay is set to be active 100% of the time, for both rising and falling currents, and prevents missed steps as shown in figure 3. if this is not an issue, it is recom- mended that automatically-selected mixed decay be used, because it will produce reduced ripple currents. refer to the fixed off-time section for details. low current microstepping. intended for applications where the minimum on-time prevents the output current from regulating to the programmed current level at low current steps. to prevent this, the device can be set to operate in mixed decay mode on both rising and falling portions of the current waveform. this feature is implemented by shorting the rosc pin to ground. in this state, the off-time is internally set to 30 s. reset input ( r e s e t ). the r e s e t input sets the translator to a predefined home state (shown in figures 8 through 11), and turns off all of the fet outputs. all step inputs are ignored until the r e s e t input is set to high. step input (step) . a low-to-high transition on the step input sequences the translator and advances the motor one incre- ment. the translator controls the input to the dacs and the direc- tion of current flow in each winding. the size of the increment is determined by the combined state of the ms1and ms2 inputs. direction input (dir). this determines the direction of rota- tion of the motor. changes to this input do not take effect until the next step rising edge. internal pwm current control. each full-bridge is con- trolled by a fixed off-time pwm current control circuit that limits the load current to a desired value, i trip . initially, a diagonal pair of source and sink fet outputs are enabled and current flows through the motor winding and the current sense resistor, r s x . when the voltage across r s x equals the dac output voltage, the current sense comparator resets the pwm latch. the latch then functional description
dmos microstepping driver with translator and overcurrent protection a4985 8 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com figure 3. continuous stepping using automatically-selected mixed stepping (rosc pin grounded) figure 2. missed steps in low-speed microstepping figure 3. continuous stepping using automatically-selected mixed stepping (rosc pin grounded) t , 1 s/div. step input 10 v/div. mixed decay no missed steps i load 500 ma/div. t , 1 s/div. step input 10 v/div. slow decay slow decay slow decay slow decay mixed decay mixed decay mixed decay mixed decay missed step voltage on rosc terminal 2 v/div.
dmos microstepping driver with translator and overcurrent protection a4985 9 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com turns off either the source fet (when in slow decay mode) or the sink and source fets (when in mixed decay mode). the maximum value of current limiting is set by the selection of r s x and the voltage at the vref pin. the transconductance func- tion is approximated by the maximum value of current limiting, i tripmax (a), which is set by i tripmax = v ref / ( 8 ? r s ) where r s is the resistance of the sense resistor ( ) and v ref is the input voltage on the ref pin (v). the dac output reduces the v ref output to the current sense comparator in precise steps, such that i trip = (%i tripmax / 100) i tripmax (see table 2 for %i tripmax at each step.) it is critical that the maximum rating (0.5 v) on the sense1 and sense2 pins is not exceeded. low current microstepping. intended for applications where the minimum on-time prevents the output current from regulating to the programmed current level at low current steps. to prevent this, the device can be set to operate in mixed decay mode on both rising and falling portions of the current waveform. this feature is implemented by shorting the rosc pin to ground. in this state, the off-time is internally set to 30 s. fixed off-time. the internal pwm current control circuitry uses a one-shot circuit to control the duration of time that the dmos fets remain off. the off-time, t off , is determined by the rosc terminal. the rosc terminal has three settings: ? rosc tied to vdd ? off-time internally set to 30 s, decay mode is automatic mixed decay except when in full step where decay mode is set to slow decay ? rosc tied directly to ground ? off-time internally set to 30 s, current decay is set to mixed decay for both increasing and decreasing currents for all step modes. ? rosc through a resistor to ground ? off-time is determined by the following formula, the decay mode is automatic mixed decay for all step modes. t off r osc 825 where t off is in s. blanking. this function blanks the output of the current sense comparators when the outputs are switched by the internal current control circuitry. the comparator outputs are blanked to prevent false overcurrent detection due to reverse recovery currents of the clamp diodes, and switching transients related to the capacitance of the load. the blank time, t blank ( s), is approximately t blank 1 s shorted-load and short-to-ground protection. if the motor leads are shorted together, or if one of the leads is shorted to ground, the driver will protect itself by sensing the overcurrent event and disabling the driver that is shorted, protect- ing the device from damage. in the case of a short-to-ground, the device will remain disabled (latched) until the s l e e p input goes high or vdd power is removed. a short-to-ground overcurrent event is shown in figure 4. when the two outputs are shorted together, the current path is through the sense resistor. after the blanking time ( 1 s) expires, the sense resistor voltage is exceeding its trip value, due to the overcurrent condition that exists. this causes the driver to go into a fixed off-time cycle. after the fixed off-time expires the driver turns on again and the process repeats. in this condition the driver is completely protected against overcurrent events, but the short is repetitive with a period equal to the fixed off-time of the driver. this condition is shown in figure 5. if the driver is operating in mixed decay mode, it is normal for the positive current to spike, due to the bridge going in the for- ward direction and then in the negative direction, as a result of the direction change implemented by the mixed decay feature. this is shown in figure 6. in both instances the overcurrent circuitry is protecting the driver and prevents damage to the device. charge pump (cp1 and cp2). the charge pump is used to generate a gate supply greater than that of vbb for driving the source-side fet gates. a 0.1 f ceramic capacitor, should be connected between cp1 and cp2. in addition, a 0.1 f ceramic capacitor is required between vcp and vbb, to act as a reservoir for operating the high-side fet gates. capacitor values should be class 2 dielectric 15% maximum, or tolerance r, according to eia (electronic industries alliance) specifications. v reg (vreg) . this internally-generated voltage is used to operate the sink-side fet outputs. the nominal output voltage of the vreg terminal is 7 v. the vreg pin must be decoupled with a 0.22 f ceramic capacitor to ground. v reg is internally monitored. in the case of a fault condition, the fet outputs of the a4985 are disabled.
dmos microstepping driver with translator and overcurrent protection a4985 10 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com capacitor values should be class 2 dielectric 15% maximum, or tolerance r, according to eia (electronic industries alliance) specifications. enable input ( e n a b l e ) . this input turns on or off all of the fet outputs. when set to a logic high, the outputs are disabled. when set to a logic low, the internal control enables the outputs as required. the translator inputs step, dir, ms1, and ms2, as well as the internal sequencing logic, all remain active, independent of the e n a b l e input state. shutdown. in the event of a fault, overtemperature (excess t j ) or an undervoltage (on vcp), the fet outputs of the a4985 are disabled until the fault condition is removed. at power-on, the uvlo (undervoltage lockout) circuit disables the fet outputs and resets the translator to the home state. sleep mode ( s l e e p ). to minimize power consumption when the motor is not in use, this input disables much of the internal circuitry including the output fets, current regulator, and charge pump. a logic low on the s l e e p pin puts the a4985 into sleep mode. a logic high allows normal operation, as well as start-up (at which time the a4985 drives the motor to the home microstep position). when emerging from sleep mode, in order to allow the charge pump to stabilize, provide a delay of 1 ms before issuing a step command. mixed decay operation. the bridge operates in mixed decay mode, depending on the step sequence, as shown in fig- ures 8 through 11. as the trip point is reached, the a4985 initially goes into a fast decay mode for 31.25% of the off-time. t off . after that, it switches to slow decay mode for the remainder of t off . a timing dagram for this feature appears on the next page. synchronous rectification . when a pwm-off cycle is triggered by an internal fixed-off-time cycle, load current recircu- lates according to the decay mode selected by the control logic. this synchronous rectification feature turns on the appropriate fets during current decay, and effectively shorts out the body diodes with the low fet r ds(on) . this reduces power dissipation significantly, and can eliminate the need for external schottky diodes in many applications. synchronous rectification turns off when the load current approaches zero (0 a), preventing reversal of the load current. t fixed off-time 5 a / div. t fault latched 5 a / div. figure 4. short-to-ground event figure 5. shorted load (outxa outxb) in slow decay mode figure 6. shorted load (outxa outxb) in mixed decay mode t 5 a / div. fixed off-time fast decay portion (direction change)
dmos microstepping driver with translator and overcurrent protection a4985 11 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com v step i out i out t see enlargement a enlargement a t sd t fd t off slow decay mixed decay fast decay i peak 70.71 C70.71 0 100.00 C100.00 symbol characteristic t off device fixed off-time i peak maximum output current t sd slow decay interval t fd fast decay interval i out device output current figure 7. current decay modes timing chart
dmos microstepping driver with translator and overcurrent protection a4985 12 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com application layout layout . the printed circuit board should use a heavy ground- plane. for optimum electrical and thermal performance, the a4985 must be soldered directly onto the board. on the under- side of the a4985 package is an exposed pad, which provides a path for enhanced thermal dissipation. the thermal pad should be soldered directly to an exposed surface on the pcb. thermal vias are used to transfer heat to other layers of the pcb. in order to minimize the effects of ground bounce and offset issues, it is important to have a low impedance single-point ground, known as a star ground , located very close to the device. by making the connection between the pad and the ground plane directly under the a4985, that area becomes an ideal location for a star ground point. a low impedance ground will prevent ground bounce during high current operation and ensure that the supply voltage remains stable at the input terminal. the two input capacitors should be placed in parallel, and as close to the device supply pins as possible. the ceramic capaci- tor (cin1) should be closer to the pins than the bulk capacitor (cin2). this is necessary because the ceramic capacitor will be responsible for delivering the high frequency current components. the sense resistors, rsx , should have a very low impedance path to ground, because they must carry a large current while supporting very accurate voltage measurements by the current sense comparators. long ground traces will cause additional voltage drops, adversely affecting the ability of the comparators to accurately measure the current in the windings. the sensex pins have very short traces to the rsx resistors and very thick, low impedance traces directly to the star ground underneath the device. if possible, there should be no other components on the sense circuits. pcb thermal vias trace (2 oz.) signal (1 oz.) ground (1 oz.) thermal (2 oz.) solder a4985 v dd v bb c2 rosc pad a4985 c6 c7 c3 c4 r4 r5 c1 out2b out1a out1b out2a vbb2 sense2 out2a out1a sense1 vbb1 out2b enable gnd cp1 cp2 vcp out1b dir gnd ref step vdd vreg ms1 ms2 reset rosc sleep r4 u1 out2b gnd r5 out2a out1a out1b gnd gnd gnd c3 c4 c6 rosc c2 c7 c1 vbb vdd capacitance bulk es package configuration shown
dmos microstepping driver with translator and overcurrent protection a4985 13 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com v dd v bb c2 rosc pad a4985 c5 c6 c3 c4 r4 r5 c1 out2b out1b out2a out1a vbb2 vbb1 dir sense2 sense1 cp1 gnd enable gnd cp2 vcp vreg rosc vdd ms1 ms2 step ref reset sleep gnd gnd gnd gnd gnd gnd gnd r4 u1 out2b gnd r5 out2a out1a out1b c3 c4 c5 rosc c2 c6 c1 vbb vdd capacitance bulk lp package typical application and circuit layout
dmos microstepping driver with translator and overcurrent protection a4985 14 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com vcp gnd cp2 gnd cp1 v bb 8 v gnd vdd gnd gnd 8 v gnd gnd 8 v v bb vreg 10 v gnd dmos parasitic sense v reg gnd vbb 40 v gnd v bb out dmos parasitic dmos parasitic gnd pgnd gnd ms1 ms2 dir vref rosc sleep pin circuit diagrams
dmos microstepping driver with translator and overcurrent protection a4985 15 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 0.00 100.00 92.39 70.71 38.27 ?38.27 ?70.71 ?92.39 ?100.00 0.00 100.00 92.39 70.71 38.27 ?38.27 ?70.71 ?92.39 ?100.00 phase 2 i out2b direction = h (%) phase 1 i out1a direction = h (%) home microstep position slow mixed slow slow mixed slow mixed slow mixed mixed step slow mixed* mixed* *with rosc p in tied to gnd figure 10. decay modes for quarter-step increments figure 9. decay modes for half-step increments figure 8. decay mode for full-step increments phase 2 i out2a direction = h (%) phase 1 i out1a direction = h (%) step home microstep position home microstep position 100.00 70.71 ?70.71 0.00 ?100.00 100.00 70.71 ?70.71 0.00 ?100.00 slow slow *with rosc pin tied to gnd home microstep position home microstep position 100.00 70.71 ?70.71 0.00 ?100.00 100.00 70.71 ?70.71 0.00 ?100.00 phase 2 i out2b direction = h (%) phase 1 i out1a direction = h (%) step slow mixed mixed* mixed* slow mixed slow mixed mixed slow mixed slow mixed slow slow dir= h dir= h dir= h
dmos microstepping driver with translator and overcurrent protection a4985 16 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com figure 11. decay modes for eighth-step increments mixed mixed slow slow mixed slow mixed slow 0.00 100.00 92.39 70.71 55.56 ?55.56 83.15 ?83.15 38.27 19.51 ?19.51 ?38.27 ?70.71 ?92.39 ?100.00 0.00 100.00 92.39 70.71 55.56 ?55.56 83.15 ?83.15 38.27 19.51 ?19.51 ?38.27 ?70.71 ?92.39 ?100.00 phase 2 i out2b direction = h (%) phase 1 i out1a direction = h (%) home microstep position step mixed* mixed* *with rosc pin tied to gnd dir= h
dmos microstepping driver with translator and overcurrent protection a4985 17 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com full step # half step # 1/4 step # 1/8 step # phase 1 current [% i tripmax ] (%) phase 2 current [% i tripmax ] (%) step angle (o) 1 1 1 100.00 0.00 0.0 2 98.08 19.51 11.3 2 3 92.39 38.27 22.5 4 83.15 55.56 33.8 1235 70.71 70.71 45.0 6 55.56 83.15 56.3 4 7 38.27 92.39 67.5 8 19.51 98.08 78.8 3 5 9 0.00 100.00 90.0 10 ?19.51 98.08 101.3 6 11 ?38.27 92.39 112.5 12 ?55.56 83.15 123.8 2 4 7 13 ?70.71 70.71 135.0 14 ?83.15 55.56 146.3 8 15 ?92.39 38.27 157.5 16 ?98.08 19.51 168.8 5 9 17 ?100.00 0.00 180.0 18 ?98.08 ?19.51 191.3 10 19 ?92.39 ?38.27 202.5 20 ?83.15 ?55.56 213.8 3 6 11 21 ?70.71 ?70.71 225.0 22 ?55.56 ?83.15 236.3 12 23 ?38.27 ?92.39 247.5 24 ?19.51 ?98.08 258.8 7 13 25 0.00 ?100.00 270.0 26 19.51 ?98.08 281.3 14 27 38.27 ?92.39 292.5 28 55.56 ?83.15 303.8 4 8 15 29 70.71 ?70.71 315.0 30 83.15 ?55.56 326.3 16 31 92.39 ?38.27 337.5 32 98.08 ?19.51 348.8 table 2. step sequencing settings home microstep position at step angle 45o; dir = h
dmos microstepping driver with translator and overcurrent protection a4985 18 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com pad 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 vbb2 sense2 out2a out1a sense1 vbb1 vreg ms1 ms2 reset rosc sleep out1b dir gnd ref step vdd out2b enable gnd cp1 cp2 vcp pin-out diagrams es package lp package 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 gnd enable out2b vbb2 sense2 out2a out1a sense1 vbb1 out1b dir gnd cp1 cp2 vcp vreg ms1 ms2 reset rosc sleep vdd step ref pad terminal list table name number description es et* lp cp1 4 7 1 charge pump capacitor terminal cp2 5 8 2 charge pump capacitor terminal dir 17 20 14 logic input e n a b l e 2 5 23 logic input gnd 3, 16 6, 19 13, 24 ground ms1 8 11 5 logic input ms2 9 12 6 logic input nc ? 2, 4, 21, 23, 26, 28, 29, 31 ? no connection out1a 21 27 18 dmos full bridge 1 output a out1b 18 24 15 dmos full bridge 1 output b out2a 22 30 19 dmos full bridge 2 output a out2b 1 1 22 dmos full bridge 2 output b ref 15 18 12 g m reference voltage input r e s e t 10 13 7 logic input rosc 11 14 8 timing set sense1 20 25 17 sense resistor terminal for bridge 1 sense2 23 32 20 sense resistor terminal for bridge 2 s l e e p 12 15 9 logic input step 14 17 11 logic input vbb1 19 22 16 load supply vbb2 24 3 21 load supply vcp 6 9 3 reservoir capacitor terminal vdd 13 16 10 logic supply vreg 7 10 4 regulator decoupling terminal pad ? ? ? exposed pad for enhanced thermal dissipation* *the gnd pins must be tied together externally by connecting to the pad ground plane under the device. pad 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 sense2 nc out2a nc nc out1a nc sense1 vcp vreg ms1 ms2 reset rosc sleep vdd out1b nc vbb1 nc dir gnd ref step out2b nc vbb2 nc enable gnd cp1 cp2 et package
dmos microstepping driver with translator and overcurrent protection a4985 19 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 0.95 c seating plane c 0.08 25x 24 24 2 1 1 2 24 2 1 a a terminal #1 mark area coplanarity includes exposed thermal pad and terminals b exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) for reference only; not for tooling use (reference jedec mo-220wggd) dimensions in millimeters exact case and lead configuration at supplier discretion within limits shown c d d c reference land pattern layout (reference ipc7351 qfn50p400x400x80-25w6m) all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) 4.10 0.30 0.50 4.10 0.50 bsc 4.00 0.15 4.00 0.15 2.70 2.70 2.70 2.70 0.75 0.05 0.45 max b pcb layout reference view 0.25 +0.05 ?0.07 es package, 24-pin qfn with exposed thermal pad
dmos microstepping driver with translator and overcurrent protection a4985 20 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com et package, 32-contact qfn with exposed thermal pad 32 32 2 1 2 1 a a terminal #1 mark area b exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) for reference only; not for tooling use (reference jedec mo-220vhhd-6) dimensions in millimeters exact case and lead configuration at supplier discretion within limits shown c reference land pattern layout (reference ipc7351 qfn50p500x500x100-33v6m); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) b 32 2 1 pcb layout reference view 3.40 3.40 0.50 bsc 5.00 0.15 5.00 0.15 0.90 0.10 0.250.10 0.500.10 3.40 3.40 0.30 1 0.50 1.00 5.00 5.00 c c 0.08 33x seating plane c d d coplanarity includes exposed thermal pad and terminals
dmos microstepping driver with translator and overcurrent protection a4985 21 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com lp package, 24-pin tssop with exposed thermal pad 1.20 max c seating plane 0.15 max c 0.10 24x 0.65 6.10 3.00 4.32 1.65 0.45 0.65 0.25 2 1 24 3.000.05 4.320.05 (1.00) gauge plane seating plane b a a terminal #1 mark area b for reference only (reference jedec mo-153 adt) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown reference land pattern layout (reference ipc7351 tsop65p640x120-25m); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) pcb layout reference view exposed thermal pad (bottom surface) c c 7.80 0.10 4.40 0.10 6.40 0.20 0.60 0.15 4 4 0.25 +0.05 ?0.06 0.15 +0.05 ?0.06
dmos microstepping driver with translator and overcurrent protection a4985 22 allegro microsystems, inc. 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com copyright ?2009-2012, allegro microsystems, inc. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com revision history revision revision date description of revision rev. 4 march 21, 2012 update example layout

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